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Updated date
Add extra flipflops to buffer output
!28
· created
Apr 21, 2017
by
Koen Zandberg
Synthesis
implementation
Merged
2
updated
Apr 21, 2017
Alu refac
!27
· created
Apr 20, 2017
by
Silke Hofstra
Synthesis
implementation
Merged
updated
Apr 21, 2017
Fix modelsim compatibility and 2002 compatibility
!25
· created
Apr 20, 2017
by
Koen Zandberg
Algorithm
implementation
lib
test
Merged
updated
Apr 20, 2017
Some cleanup for report
!22
· created
Apr 20, 2017
by
Silke Hofstra
Algorithm
implementation
lib
test
Merged
2
updated
Apr 20, 2017
It did optimization
!21
· created
Apr 20, 2017
by
Koen Zandberg
implementation
Merged
updated
Apr 20, 2017
Implementation test
!20
· created
Apr 20, 2017
by
Silke Hofstra
Algorithm
implementation
test
Merged
updated
Apr 20, 2017
Let the muxer handle the memory
!18
· created
Apr 20, 2017
by
Silke Hofstra
implementation
test
Merged
updated
Apr 20, 2017
Improved decoder structure
!19
· created
Apr 20, 2017
by
Koen Zandberg
implementation
Merged
updated
Apr 20, 2017
Split asynchronous logic
!17
· created
Apr 19, 2017
by
Silke Hofstra
implementation
Merged
updated
Apr 19, 2017
Create test and improve muxer
!16
· created
Apr 19, 2017
by
Silke Hofstra
implementation
test
Merged
updated
Apr 19, 2017
Properly fix asynchronous working of register map
!15
· created
Apr 19, 2017
by
Koen Zandberg
implementation
Merged
updated
Apr 19, 2017
Add register test and modify types to match new coding style
!14
· created
Apr 19, 2017
by
Koen Zandberg
implementation
test
Merged
updated
Apr 19, 2017
Initial decode.
!12
· created
Apr 19, 2017
by
Koen Zandberg
implementation
Merged
updated
Apr 19, 2017
ALU
!10
· created
Apr 18, 2017
by
Silke Hofstra
implementation
test
Merged
10
updated
Apr 19, 2017
Add register map implementation
!8
· created
Apr 04, 2017
by
Koen Zandberg
implementation
Merged
updated
Apr 04, 2017